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Consultant at Silynx Communications, Rockville, MD (November 09 to July 10)
Redesigned the power supply and analog circuitry for the C4OPS, the company's main product. I also designed the analog and
digital circuitry for the GRIP product. This involved 3 PCBs with Analog, Digital and Mixed Signal circuitry. The Communications
Board used a ZIGBEE short range RF link.
Designed a miniature power supply to operate a C4OPS remote from a coin cell. Designed two amplifier circuits to interface the
C4OPS to alternate headsets.
Contract at ARINC, Annapolis, MD (August 09 to October 09)
Modified the VHDL code on an off the shelf video processing board. One was an “Endian” swap to interface with the off the shelf
processor board. The other was a signal processing function to combine the pixels of multiple scan lines into “bins” to enhance
the image.
Contract at DRS C-3 Systems, Gaithersburg, MD (March 09 to July 09)
Designed a PCB for a test fixture. This involved mixed signal (analog and digital) circuitry to interface an off the shelf digital IO
card to a proprietary FPGA board (the Unit Under Test). The design utilized an A to D converter (running at 100 MHz) to measure
peak waveform levels, high speed comparators and a D to A converter for waveform generation.
Contract with Optical Air Data Systems (December 08 to January 09)
Worked on an analog/digital module for the health monitoring system for the Vindicator Laser Wind Sensor health monitoring
system. The analog part of the system captured the amplitude of a pulse from a photodiode detector which was digitized by an A
to D converter. The module used High speed Op Amps and Shottky diodes. Design was done with ORCAD and the analog part
was simulated with PSPICE.
Contract with Hamilton Sunstrand, Rockford IL (June 08 to December 08)
Worked on the power control system for the NASA Orion Spacecraft. Starting with high level system design and vague
requirements created more detailed block diagrams and flow diagrams of Gigabit Ethernet interface. Wrote VHDL for a
simulator to test out this interface. Finialized Module Requirements Document (MRD) for the Power Control Module FPGA.
Document was written and reviewed per the DO254 standard.
Contract with Advanced Sensors Research and Development (March 08 to April 08)
Designed three PCB for ASR&Ds proof of concept demonstration. This involved Digital and Analog design, including some RF
design for the 250 MHz link to the remote sensor subsystem,and some analog signal processing (using Operational Amplifiers).
Researched and selected the schematic capture tool and the PCB layout tool. I also selected all the components for the three
PCBs and engineering component kits for tweaking circuits during engineering test.
Contract with Ballard Power Systems in College Park, MD (October 07 to December 07)
Did preliminary system level design for a Fuel Cell Hybrid Battery project. Designed the Operator interface, researched main
cooling fan and selected capital equipment list for setting up the Lab.
Contract at Thalus Communications, Clarksburg MD (February 07 to June 07)
Designed two PCBs for the Multichannel, MultiApplication Relay (MMAR) project. This provided the interface from an aircraft to the
user ports of two JTARS Enhanced MBITR (JEM) radios. It also contained provision for putting the radios in the “retransmit” Mode
in which the radios are used as a relay. Designed the circuitry (in ORCAD), supervised the PCB layout and bench tested the
prototypes. This was a quick turnaround project based heavily on the existing Watchkeeper project. Changes mostly consisted
of adding a second radio and implementing the Retransmit function.
Contract at Hughes Network Systems, Gaithersburg MD (September 06 to January 07)
Designed three modules for a satellite communications system using the VERILOG Hardware Description Language. These
were an IRIG-B module to extract timing data from an IRIG-B data stream and two correlation blocks for other parts of the
communications system. This design was targeted to an XILINX Virtex-4 FPGA, and extensive use was made of the Memory and
DSP blocks in the FPGA. Coregen was used to customise these general purpose blocks into Dual Port RAMs of various
configurations, Adders and Multipliers.
Designed modules, wrote test benches, simulated design and did preliminary place and route (using Synplify) to check design.
Contract at Kaman Fuzing, Middletown CT (May 06 to September 06)
Redesigned a fuze using good design practices so as to improve robustness and reliability. This design was implemented in
an Actel A42MX16 anti-fuse FPGA. FPGA design was done in Orcad, using special symbols. The equivalent schematic was than
converted to VHDL for simulation and synthesis. Did a hierarchical design, simulating each sub-block individually and then
simulating the entire design. Wrote testbenches for the simulations in VHDL. And simulated using Modelsim. Synthesis, place
and route was done with Libero (Actel’s synthesis tool).
Analyzed the existing design, put together a PowerPoint presentation outlining the changes I recommended. Made the changes
and verified the design by simulation. Wrote a Theory of Operation for the entire product (FPGA and external circuitry) and
prepared documents for a “Tech Assist” with the customer.
Contract at ITT Space Systems Division, Fort Wayne, IN (August 05 to February 06)
Assisted in debugging the Receiver Interface Board for a satellite radio receiver. Found and corrected bugs in the linear regulator
circuit. Later simulated the circuit for a worst case analysis, using the Cadence AMS (P-Spice) simulator with Orcad Capture as
the front end.
Researched and specified off the shelf components to construct a test bed for evaluating two different SpaceWire solutions. This
used the compact PCI (cPCI) bus.
Wrote a test plan for the Video Processor of the Advanced Baseline Imager (ABI), an earth sensing system for the National
Oceanic and Atmospheric Administration (NOAA). The contract was administered through NASA.
Wrote VHDL code for testing an ABI brassboard. The PCB used an Actel A1280 FPGA.
Contract at Goddard Space Flight Center, Greenbelt, MD (February 05 to June 05)
Designed the Interface between the compact PCI (cPCI) bus and the Robot Arm for the Ejection Module of the Hubble Rescue
Vehicle (HRV). Logic design was done in VHDL, compiled with Symplify Pro version 8.0 and simulated with ModelSim PE,
version 6.0c.
Reviewed the schematics for the Ku Band Communications Card for the HRV, designed the cPCI interface and the power
distribution system for it. Participated in system design work for a redundant processor card which used a Power PC 405 core in
a Virtex II pro Xilinx FPGA (XC2VPX70).
Researched use of power and ground planes as embedded capacitors, and PCB materials useful for this purpose.
Contract at Goodrich Fuel and Utility Systems, Vergennes, VT (March 04 to January 05)
Designed an improved power supply for the Health and Usage Monitoring System (HUMS) to increase efficiency and reduce
cost. Making maximum use of off the shelf components, the new power supply increased efficiency from ~50% to ~80% while
reducing the materials cost by half. Wrote the performance specification, captured the schematic (using Veribest), performed
component stress analysis, and performed reliability analysis (using Relex 7.5).
Finished the design of the backplane for the HUMS system. Was assigned to the design of the Bearing Monitor Unit, which was
far behind schedule. Captured the schematic, and redesigned much of the circuitry to reduce size and power consumption.
Worked with the PCB designers to get the boards placed and routed. The analog design included interfaces for accelerometers,
synchros and RTD temperature sensors. The digital portion used a Motorola MPC5200 (Power PC).
While the HUMS is intended primarily for military helicopters, it was designed to best commercial practices.
Contract at DRS Signal Recording Technologies, Columbia MD (April 03 to September 03)
Designed an RS422 interface for the Eagle Data Recorder which operates at a bit rate of 30 Mb/s. Designed the RS422
Baseboard which contained the RS 422 interface circuitry, the XILINX XCV300E FPGA, and the interface to the Eagle system.
Also designed two daughter boards for the RS422 interface. One just had expansion connectors, the other had two Analog
Devices AD9854 Direct Digital Synthesis ICs. Simulated the design of the output filters for the DDS using RFsim99.
The DDS daughter board also included a Switched Mode Power Supply (SMPS) to regulate the 5 volts from the system to 3.3
Volts. Used the APLAC circuit simulation tool to analyze the waveforms in SMPS design.
Designed a DDS daughter board for a different part of the system which had six AD9854 chips. This required a SMPS to provide
3.3 volts from a 3.3 volt supply which was insufficiently well regulated (there was insufficient time to redesign the mainframe
power supply). This was designed with the Single Ended Primary Inductance Converter (SEPIC) architecture (using an LM3478).
Dorsal Networks, Columbia, MD (May 02 to Jamuary 03)
Participated in the design and development of the Line Unit (submerged repeater) for Dorsal’s optical networking system.
Specifically worked on digital design and simulation of the APEX FPGA (Altera EP20K200EQC240) for the Line Unit internal
communications system, and the high efficiency Pump Laser Driver PCB.
FPGA code was written in VHDL, simulated with ModelSim, compiled with Exemplar’s Leonardo Spectrum, and fitted with Altera
Quartus II. Laser Driver board was a modification of the existing Linear Regulator board, replacing the linear regulator with a
Switched Mode Power Supply to reduce waste heat, and using A/D and D/A converters for feedback control. Modified schematics,
supervised PCB designer on layout and routing, and conducted design reviews.
Contract at Corvis, Baylight Division, Columbia, MD (August 01 to February 02)
Participated in design and development of several subsystems of the Optical Convergence Switch (OCS) which is the part of the
Corvis networking system which interfaces the optical network to existing copper based networks. This included the ODC-48
Daughterboard, which does the optical to electrical interface for the system. This was designed as a daughterboard to allow a
customer to start small, and grow the system as needed. Took over the project, made modifications, and saw it through a re-
spin. Also found a second source for the optical transceiver.
Developed the Synchronization Board. This provided a path for the Building-Integrated Timing Source (BITS) input to the
switching matrix. Starting with a set of requirements, I researched and selected components, designed the circuitry (using
VeriBest), designed the PCB (using Expedition PCB), and generated the output files for the PCB fabrication. I did the PC design
because of a tight schedule and a shortage of PCB designers.
Contract at Arbitron, Columbia, MD (May 01 to August 01)
Design of Digital Encoder for the Portable People Meter involved designing to Digital Audio standards (domestic and EU),
selecting components, schematic capture using ORCAD, and coding of an Altera EPM22 FPGA in VHDL. In addition, reviewed
two other designs for accuracy and completeness, offering suggestions about Design Practices, Reliability, and Signal Integrity.
Designed a DC to DC converter for one of the designs, which emphasized design for reuse.
Contract at Motorola ASAP, Germantown, MD (January 01 to April 01)
Assisted in writing, simulating and testing Verilog code for an ASIC which was being developed for one of Motorola
Semiconductor’s customers. Designed FPGA based emulation board which was used to test the VHDL and to develop and test
software for the embedded microprocessor. Assisted in test of the emulation board.
Contract at Northrop Grumman, Linthicum, MD (November 00 to January 01)
Helped prepare and present the Sonar Pre Processing subsystem of the Baseband Sonar Advanced Receiver at the Project’s
Preliminary Design Review. Began detail design of circuitry, which used 12 32 bit DSP processors (Analog Devices ADSP-
21160). Analyzed requirements, selected components, and drew the schematic (using Mentor Graphics Design Architect) for the
three DSP clusters, the control microprocessor and the I/O buffers. Used placeholders for the four FPGAs and the two CPLDs
which constituted the rest of the design.
Contract at Litton Advanced Systems, College Park, MD (February 99 to November 00)
Designing two Printed Circuit Boards (PCB) for a major electronics upgrade to the EA6-B Aircraft. Both PCBs use a VME64x
interface for data transfer and for I/O signals (using the user defined pins).
For the Interface Control Unit, I wrote the specification, researched and selected components, drew block diagrams, wrote the
Engineering Information, performed the detail circuit design, wrote the FPGA programming code (in VHDL), and advised Test
Engineering on test related issues. Designed analog circuitry for audio signal processing and filtering. Designed video
bandwidth Bessel filters (to minimize phase distortion) using current feedback Op-Amps to achieve the necessary bandwidth.
For the Master Blanking Unit, I edited the specification, researched and selected components, drew block diagrams, wrote the
Engineering Information, performed the detail circuit design, wrote the FPGA programming code (in VHDL), and advised Test
Engineering on test related issues.
Contract at Raytheon Systems communications division, Towson, MD (February 98 to January 99)
Modified the programming of the Xilinx FPGAs on two PCBs in an Identification Friend or Foe (IFF) system which was being
modified for civilian use. The existing Schematics were done with schematic capture (Mentor Graphics Design Architect).
Modified the schematics where appropriate, and wrote or modified new functions in VHDL. Simulated the resulting design to
confirm proper operation
Designed a PCB for a next generation military IFF system, including Component Selection, Detail Design, Coordination with PCB
designer, and FPGA programming.
Contract at Litton Advanced Systems, College Park, MD (April 97 to December 97)
Designed two subsystems for a data processing system. These designs were mostly implemented in XILINX FPGAs. One was
designed with Mentor Graphics Design Architect, the other with XILINX Foundation Series CAE tools using a combination of
schematic capture and VHDL coded modules.
Performed preliminary design and component selection for a satellite project, which required radiation hardened and radiation
tolerant components. This project used an Actel anti-fuse gate array for greater radiation tolerance.
Contract at Frederick Engineering, Columbia MD (November 96 to March 97)
Designed, developed, debugged and tested three interfaces for the P2000 Protocol analyzer. These were for the ISDN U
interface (Digital Subscriber Line), the ISDN S/T interface, and DDS interface. This involved circuit design done on ORCAD for
Windows and ALTERA MAXPLUS2 design for 7000 and 10,000 series devices. One of the interfaces required impedance
buffering to avoid loading the line. Designed and implemented an Op-Amp circuit for this purpose.
Contract at Northrop Grumman, Electronic Systems and Sensors, Linthicum, MD (Jan 96 to Nov 96)
Designed two interfaces for a VME Bus based data collection system. One was for an infrared sensor, the other for a MIL STD
1553 data communications bus. The designs were implemented with standard logic, XILINX FPGAs, and ALTERA 8000 series
FPGAs. The ALTERA FPGA designs were done with MAXPLUS2 design software, using both graphical and ALTERA HDL (AHDL)
design files.
Contract at Telecommunications Techniques Corporation, Germantown, MD (Nov 94 to Jan 95)
Designed and coded (in Verilog) the digital circuitry for a Direct Digital Service (DDS) board, which was part of a digital
telecommunications test set. This was implemented in a XILINX FPGA. Took over a partially completed project, and carried it
through to completion. Wrote the Verilog code for the unimplemented portion of the design, compiled, debugged, and simulated
the entire design.
Contract at SWL Telecommunications Division, Columbia, MD (July 94 to November 94)
Designed a multiprocessor system which employed a Motorola MC68040, one MC68360 Communications processor in the
companion mode, and two more 68360s in the slave mode. This was the controller for a SONET/SDH OC3 device, which could
act as a repeater, a demarcation point "Firewall", a SONET/SDH translator, and a translating interface between incompatible
SONET network devices. The design involved Fast Page Mode DRAMs for burst mode cache filling, FLASH memory for code
storage, Non-Volatile RAM for parameter storage, real time clock, and ALTERA 7000 series CPLDs for glue logic. Design was
done on Cadence design tools, hosted on SUN workstations.
Contract at Hughes Network Systems, Gaithersburg, MD (July 93 to July 94)
Designed the Channel Coding Hardware for a satellite modem. This included data scrambling, BPSK, QPSK, and 8PSK
differential encoding, convolutional coding and Viterbi decoding, sequential coding, Reed Solomon coding, V.35 scrambling,
received signal synchronization, overhead channel insertion and extraction, and rate puncturing. Design was implemented using
XILINX 4000 FPGAs. Designed part of microprocessor control circuitry and implemented it in an Actel gate array.
TV Answer, Reston, Virginia (May 92 to November 93)
Designed controller for a VHF transceiver which was part of a cellular data link. This utilized an 80C51 micro controller, FIFOs,
and programmable logic. Developed three options for the programmable logic; PLDs (using ABEL), MACH high density
programmable logic (using PALASM), and XILINX programmable gate arrays (using XACT).
Telematics, Herndon, Virginia (August 91 to February 92)
Performed sustaining work on a 68030 based T1 Multiplexer. Evaluated multiple RISC processors for an embedded control
application. Designed RISC processor board for a Frame Relay product to enhance performance. Prepared technical proposal
for Direct Digital Service (DDS) interface for existing system. Performed preliminary architecture study for next generation
equipment which would use Fiber Optic trunks. Represented the company at meetings of an IEEE SONET/SDH working group.
DENRO, Gaithersburg, Maryland (April 88 to March 91)
Designed multiplexer subsystem of DENRO's digital voice switch. The design involved national and international
telecommunications standards, and high speed digital design using PLDs, Advanced CMOS, FAST, HC, and ECL. Provided
technical supervision of two technicians and a junior engineer, and acted as a technical resource to the junior members of the R
and D team. Implemented the PLD documentation system. Developed a Radio Interface processor board to connect the digital
voice switch to air traffic control radios and a Telephone Interface/Operator Position processor board. These designs utilized the
80C188 microprocessor, and CODECs for the analog/digital and digital/analog interface.
AGB Television Research, Columbia, Maryland (10 mos.)
Managed the Design, Development, and Production of the major in home subsystem of AGB's automated remote data collection
system. This product was based on an 80C88, and used an auto-dial telephone line MODEM, and a current carrier MODEM, and
battery backed up RAM for temporary data storage. Performed system level and detail design. Responsible for contacting,
interviewing, and selecting vendors for PCB design, PCB fabrication, Assembly, and Parts Kiting. Provided technical
management for a technician and a junior engineer.
Fairchild Communications and Electronics, Germantown, Maryland (2 years)
Designed, developed, and debugged three subsystems of an aircraft camera controller. Extensive use was made of
Programmable Logic Devices to meet density and flexibility requirements. Responsibilities also included worst case timing
analysis, testability analysis, and Built-In-Test design and analysis.
Compression Techniques Corporation, Vienna, Virginia (6 months)
Managed the design and development of the Digital Access and Cross Connect system, which switched and combined up to 64
T1 streams. Performed overall system specification, design, and architecture, and detail design of the switching matrix, system
timing, and fault detection. Selected master CPU (80C86) and supervised detail design of the T1 interface unit. Supervised a
junior engineer and a technician in addition to being an individual contributor.
Access Engineering Corporation, Reston, Virginia (18 months)
Designed direct sequence Spread Spectrum modulator for a 2400 BPS data-over-voice (DOV) MODEM. Designed and
developed a 19.2 KBPS PSK DOV MODEM, which provided for integration of the spread spectrum modulator. Also, performed
preliminary design for an 80 KBPS DOV MODEM as a transitional ISDN product.
RIXON, Inc., Silver Spring, Maryland (2 years)
Designed telecommunications Modems including LSI/MSI digital design, embedded processors, analog signal processing, and
A/D and D/A conversion. Managed product development projects, which involved product definition, planning, generation of
schedules and budgets, and tracking project progress.
Redesigned the power supply and analog circuitry for the C4OPS, the company's main product. I also designed the analog and
digital circuitry for the GRIP product. This involved 3 PCBs with Analog, Digital and Mixed Signal circuitry. The Communications
Board used a ZIGBEE short range RF link.
Designed a miniature power supply to operate a C4OPS remote from a coin cell. Designed two amplifier circuits to interface the
C4OPS to alternate headsets.
Contract at ARINC, Annapolis, MD (August 09 to October 09)
Modified the VHDL code on an off the shelf video processing board. One was an “Endian” swap to interface with the off the shelf
processor board. The other was a signal processing function to combine the pixels of multiple scan lines into “bins” to enhance
the image.
Contract at DRS C-3 Systems, Gaithersburg, MD (March 09 to July 09)
Designed a PCB for a test fixture. This involved mixed signal (analog and digital) circuitry to interface an off the shelf digital IO
card to a proprietary FPGA board (the Unit Under Test). The design utilized an A to D converter (running at 100 MHz) to measure
peak waveform levels, high speed comparators and a D to A converter for waveform generation.
Contract with Optical Air Data Systems (December 08 to January 09)
Worked on an analog/digital module for the health monitoring system for the Vindicator Laser Wind Sensor health monitoring
system. The analog part of the system captured the amplitude of a pulse from a photodiode detector which was digitized by an A
to D converter. The module used High speed Op Amps and Shottky diodes. Design was done with ORCAD and the analog part
was simulated with PSPICE.
Contract with Hamilton Sunstrand, Rockford IL (June 08 to December 08)
Worked on the power control system for the NASA Orion Spacecraft. Starting with high level system design and vague
requirements created more detailed block diagrams and flow diagrams of Gigabit Ethernet interface. Wrote VHDL for a
simulator to test out this interface. Finialized Module Requirements Document (MRD) for the Power Control Module FPGA.
Document was written and reviewed per the DO254 standard.
Contract with Advanced Sensors Research and Development (March 08 to April 08)
Designed three PCB for ASR&Ds proof of concept demonstration. This involved Digital and Analog design, including some RF
design for the 250 MHz link to the remote sensor subsystem,and some analog signal processing (using Operational Amplifiers).
Researched and selected the schematic capture tool and the PCB layout tool. I also selected all the components for the three
PCBs and engineering component kits for tweaking circuits during engineering test.
Contract with Ballard Power Systems in College Park, MD (October 07 to December 07)
Did preliminary system level design for a Fuel Cell Hybrid Battery project. Designed the Operator interface, researched main
cooling fan and selected capital equipment list for setting up the Lab.
Contract at Thalus Communications, Clarksburg MD (February 07 to June 07)
Designed two PCBs for the Multichannel, MultiApplication Relay (MMAR) project. This provided the interface from an aircraft to the
user ports of two JTARS Enhanced MBITR (JEM) radios. It also contained provision for putting the radios in the “retransmit” Mode
in which the radios are used as a relay. Designed the circuitry (in ORCAD), supervised the PCB layout and bench tested the
prototypes. This was a quick turnaround project based heavily on the existing Watchkeeper project. Changes mostly consisted
of adding a second radio and implementing the Retransmit function.
Contract at Hughes Network Systems, Gaithersburg MD (September 06 to January 07)
Designed three modules for a satellite communications system using the VERILOG Hardware Description Language. These
were an IRIG-B module to extract timing data from an IRIG-B data stream and two correlation blocks for other parts of the
communications system. This design was targeted to an XILINX Virtex-4 FPGA, and extensive use was made of the Memory and
DSP blocks in the FPGA. Coregen was used to customise these general purpose blocks into Dual Port RAMs of various
configurations, Adders and Multipliers.
Designed modules, wrote test benches, simulated design and did preliminary place and route (using Synplify) to check design.
Contract at Kaman Fuzing, Middletown CT (May 06 to September 06)
Redesigned a fuze using good design practices so as to improve robustness and reliability. This design was implemented in
an Actel A42MX16 anti-fuse FPGA. FPGA design was done in Orcad, using special symbols. The equivalent schematic was than
converted to VHDL for simulation and synthesis. Did a hierarchical design, simulating each sub-block individually and then
simulating the entire design. Wrote testbenches for the simulations in VHDL. And simulated using Modelsim. Synthesis, place
and route was done with Libero (Actel’s synthesis tool).
Analyzed the existing design, put together a PowerPoint presentation outlining the changes I recommended. Made the changes
and verified the design by simulation. Wrote a Theory of Operation for the entire product (FPGA and external circuitry) and
prepared documents for a “Tech Assist” with the customer.
Contract at ITT Space Systems Division, Fort Wayne, IN (August 05 to February 06)
Assisted in debugging the Receiver Interface Board for a satellite radio receiver. Found and corrected bugs in the linear regulator
circuit. Later simulated the circuit for a worst case analysis, using the Cadence AMS (P-Spice) simulator with Orcad Capture as
the front end.
Researched and specified off the shelf components to construct a test bed for evaluating two different SpaceWire solutions. This
used the compact PCI (cPCI) bus.
Wrote a test plan for the Video Processor of the Advanced Baseline Imager (ABI), an earth sensing system for the National
Oceanic and Atmospheric Administration (NOAA). The contract was administered through NASA.
Wrote VHDL code for testing an ABI brassboard. The PCB used an Actel A1280 FPGA.
Contract at Goddard Space Flight Center, Greenbelt, MD (February 05 to June 05)
Designed the Interface between the compact PCI (cPCI) bus and the Robot Arm for the Ejection Module of the Hubble Rescue
Vehicle (HRV). Logic design was done in VHDL, compiled with Symplify Pro version 8.0 and simulated with ModelSim PE,
version 6.0c.
Reviewed the schematics for the Ku Band Communications Card for the HRV, designed the cPCI interface and the power
distribution system for it. Participated in system design work for a redundant processor card which used a Power PC 405 core in
a Virtex II pro Xilinx FPGA (XC2VPX70).
Researched use of power and ground planes as embedded capacitors, and PCB materials useful for this purpose.
Contract at Goodrich Fuel and Utility Systems, Vergennes, VT (March 04 to January 05)
Designed an improved power supply for the Health and Usage Monitoring System (HUMS) to increase efficiency and reduce
cost. Making maximum use of off the shelf components, the new power supply increased efficiency from ~50% to ~80% while
reducing the materials cost by half. Wrote the performance specification, captured the schematic (using Veribest), performed
component stress analysis, and performed reliability analysis (using Relex 7.5).
Finished the design of the backplane for the HUMS system. Was assigned to the design of the Bearing Monitor Unit, which was
far behind schedule. Captured the schematic, and redesigned much of the circuitry to reduce size and power consumption.
Worked with the PCB designers to get the boards placed and routed. The analog design included interfaces for accelerometers,
synchros and RTD temperature sensors. The digital portion used a Motorola MPC5200 (Power PC).
While the HUMS is intended primarily for military helicopters, it was designed to best commercial practices.
Contract at DRS Signal Recording Technologies, Columbia MD (April 03 to September 03)
Designed an RS422 interface for the Eagle Data Recorder which operates at a bit rate of 30 Mb/s. Designed the RS422
Baseboard which contained the RS 422 interface circuitry, the XILINX XCV300E FPGA, and the interface to the Eagle system.
Also designed two daughter boards for the RS422 interface. One just had expansion connectors, the other had two Analog
Devices AD9854 Direct Digital Synthesis ICs. Simulated the design of the output filters for the DDS using RFsim99.
The DDS daughter board also included a Switched Mode Power Supply (SMPS) to regulate the 5 volts from the system to 3.3
Volts. Used the APLAC circuit simulation tool to analyze the waveforms in SMPS design.
Designed a DDS daughter board for a different part of the system which had six AD9854 chips. This required a SMPS to provide
3.3 volts from a 3.3 volt supply which was insufficiently well regulated (there was insufficient time to redesign the mainframe
power supply). This was designed with the Single Ended Primary Inductance Converter (SEPIC) architecture (using an LM3478).
Dorsal Networks, Columbia, MD (May 02 to Jamuary 03)
Participated in the design and development of the Line Unit (submerged repeater) for Dorsal’s optical networking system.
Specifically worked on digital design and simulation of the APEX FPGA (Altera EP20K200EQC240) for the Line Unit internal
communications system, and the high efficiency Pump Laser Driver PCB.
FPGA code was written in VHDL, simulated with ModelSim, compiled with Exemplar’s Leonardo Spectrum, and fitted with Altera
Quartus II. Laser Driver board was a modification of the existing Linear Regulator board, replacing the linear regulator with a
Switched Mode Power Supply to reduce waste heat, and using A/D and D/A converters for feedback control. Modified schematics,
supervised PCB designer on layout and routing, and conducted design reviews.
Contract at Corvis, Baylight Division, Columbia, MD (August 01 to February 02)
Participated in design and development of several subsystems of the Optical Convergence Switch (OCS) which is the part of the
Corvis networking system which interfaces the optical network to existing copper based networks. This included the ODC-48
Daughterboard, which does the optical to electrical interface for the system. This was designed as a daughterboard to allow a
customer to start small, and grow the system as needed. Took over the project, made modifications, and saw it through a re-
spin. Also found a second source for the optical transceiver.
Developed the Synchronization Board. This provided a path for the Building-Integrated Timing Source (BITS) input to the
switching matrix. Starting with a set of requirements, I researched and selected components, designed the circuitry (using
VeriBest), designed the PCB (using Expedition PCB), and generated the output files for the PCB fabrication. I did the PC design
because of a tight schedule and a shortage of PCB designers.
Contract at Arbitron, Columbia, MD (May 01 to August 01)
Design of Digital Encoder for the Portable People Meter involved designing to Digital Audio standards (domestic and EU),
selecting components, schematic capture using ORCAD, and coding of an Altera EPM22 FPGA in VHDL. In addition, reviewed
two other designs for accuracy and completeness, offering suggestions about Design Practices, Reliability, and Signal Integrity.
Designed a DC to DC converter for one of the designs, which emphasized design for reuse.
Contract at Motorola ASAP, Germantown, MD (January 01 to April 01)
Assisted in writing, simulating and testing Verilog code for an ASIC which was being developed for one of Motorola
Semiconductor’s customers. Designed FPGA based emulation board which was used to test the VHDL and to develop and test
software for the embedded microprocessor. Assisted in test of the emulation board.
Contract at Northrop Grumman, Linthicum, MD (November 00 to January 01)
Helped prepare and present the Sonar Pre Processing subsystem of the Baseband Sonar Advanced Receiver at the Project’s
Preliminary Design Review. Began detail design of circuitry, which used 12 32 bit DSP processors (Analog Devices ADSP-
21160). Analyzed requirements, selected components, and drew the schematic (using Mentor Graphics Design Architect) for the
three DSP clusters, the control microprocessor and the I/O buffers. Used placeholders for the four FPGAs and the two CPLDs
which constituted the rest of the design.
Contract at Litton Advanced Systems, College Park, MD (February 99 to November 00)
Designing two Printed Circuit Boards (PCB) for a major electronics upgrade to the EA6-B Aircraft. Both PCBs use a VME64x
interface for data transfer and for I/O signals (using the user defined pins).
For the Interface Control Unit, I wrote the specification, researched and selected components, drew block diagrams, wrote the
Engineering Information, performed the detail circuit design, wrote the FPGA programming code (in VHDL), and advised Test
Engineering on test related issues. Designed analog circuitry for audio signal processing and filtering. Designed video
bandwidth Bessel filters (to minimize phase distortion) using current feedback Op-Amps to achieve the necessary bandwidth.
For the Master Blanking Unit, I edited the specification, researched and selected components, drew block diagrams, wrote the
Engineering Information, performed the detail circuit design, wrote the FPGA programming code (in VHDL), and advised Test
Engineering on test related issues.
Contract at Raytheon Systems communications division, Towson, MD (February 98 to January 99)
Modified the programming of the Xilinx FPGAs on two PCBs in an Identification Friend or Foe (IFF) system which was being
modified for civilian use. The existing Schematics were done with schematic capture (Mentor Graphics Design Architect).
Modified the schematics where appropriate, and wrote or modified new functions in VHDL. Simulated the resulting design to
confirm proper operation
Designed a PCB for a next generation military IFF system, including Component Selection, Detail Design, Coordination with PCB
designer, and FPGA programming.
Contract at Litton Advanced Systems, College Park, MD (April 97 to December 97)
Designed two subsystems for a data processing system. These designs were mostly implemented in XILINX FPGAs. One was
designed with Mentor Graphics Design Architect, the other with XILINX Foundation Series CAE tools using a combination of
schematic capture and VHDL coded modules.
Performed preliminary design and component selection for a satellite project, which required radiation hardened and radiation
tolerant components. This project used an Actel anti-fuse gate array for greater radiation tolerance.
Contract at Frederick Engineering, Columbia MD (November 96 to March 97)
Designed, developed, debugged and tested three interfaces for the P2000 Protocol analyzer. These were for the ISDN U
interface (Digital Subscriber Line), the ISDN S/T interface, and DDS interface. This involved circuit design done on ORCAD for
Windows and ALTERA MAXPLUS2 design for 7000 and 10,000 series devices. One of the interfaces required impedance
buffering to avoid loading the line. Designed and implemented an Op-Amp circuit for this purpose.
Contract at Northrop Grumman, Electronic Systems and Sensors, Linthicum, MD (Jan 96 to Nov 96)
Designed two interfaces for a VME Bus based data collection system. One was for an infrared sensor, the other for a MIL STD
1553 data communications bus. The designs were implemented with standard logic, XILINX FPGAs, and ALTERA 8000 series
FPGAs. The ALTERA FPGA designs were done with MAXPLUS2 design software, using both graphical and ALTERA HDL (AHDL)
design files.
Contract at Telecommunications Techniques Corporation, Germantown, MD (Nov 94 to Jan 95)
Designed and coded (in Verilog) the digital circuitry for a Direct Digital Service (DDS) board, which was part of a digital
telecommunications test set. This was implemented in a XILINX FPGA. Took over a partially completed project, and carried it
through to completion. Wrote the Verilog code for the unimplemented portion of the design, compiled, debugged, and simulated
the entire design.
Contract at SWL Telecommunications Division, Columbia, MD (July 94 to November 94)
Designed a multiprocessor system which employed a Motorola MC68040, one MC68360 Communications processor in the
companion mode, and two more 68360s in the slave mode. This was the controller for a SONET/SDH OC3 device, which could
act as a repeater, a demarcation point "Firewall", a SONET/SDH translator, and a translating interface between incompatible
SONET network devices. The design involved Fast Page Mode DRAMs for burst mode cache filling, FLASH memory for code
storage, Non-Volatile RAM for parameter storage, real time clock, and ALTERA 7000 series CPLDs for glue logic. Design was
done on Cadence design tools, hosted on SUN workstations.
Contract at Hughes Network Systems, Gaithersburg, MD (July 93 to July 94)
Designed the Channel Coding Hardware for a satellite modem. This included data scrambling, BPSK, QPSK, and 8PSK
differential encoding, convolutional coding and Viterbi decoding, sequential coding, Reed Solomon coding, V.35 scrambling,
received signal synchronization, overhead channel insertion and extraction, and rate puncturing. Design was implemented using
XILINX 4000 FPGAs. Designed part of microprocessor control circuitry and implemented it in an Actel gate array.
TV Answer, Reston, Virginia (May 92 to November 93)
Designed controller for a VHF transceiver which was part of a cellular data link. This utilized an 80C51 micro controller, FIFOs,
and programmable logic. Developed three options for the programmable logic; PLDs (using ABEL), MACH high density
programmable logic (using PALASM), and XILINX programmable gate arrays (using XACT).
Telematics, Herndon, Virginia (August 91 to February 92)
Performed sustaining work on a 68030 based T1 Multiplexer. Evaluated multiple RISC processors for an embedded control
application. Designed RISC processor board for a Frame Relay product to enhance performance. Prepared technical proposal
for Direct Digital Service (DDS) interface for existing system. Performed preliminary architecture study for next generation
equipment which would use Fiber Optic trunks. Represented the company at meetings of an IEEE SONET/SDH working group.
DENRO, Gaithersburg, Maryland (April 88 to March 91)
Designed multiplexer subsystem of DENRO's digital voice switch. The design involved national and international
telecommunications standards, and high speed digital design using PLDs, Advanced CMOS, FAST, HC, and ECL. Provided
technical supervision of two technicians and a junior engineer, and acted as a technical resource to the junior members of the R
and D team. Implemented the PLD documentation system. Developed a Radio Interface processor board to connect the digital
voice switch to air traffic control radios and a Telephone Interface/Operator Position processor board. These designs utilized the
80C188 microprocessor, and CODECs for the analog/digital and digital/analog interface.
AGB Television Research, Columbia, Maryland (10 mos.)
Managed the Design, Development, and Production of the major in home subsystem of AGB's automated remote data collection
system. This product was based on an 80C88, and used an auto-dial telephone line MODEM, and a current carrier MODEM, and
battery backed up RAM for temporary data storage. Performed system level and detail design. Responsible for contacting,
interviewing, and selecting vendors for PCB design, PCB fabrication, Assembly, and Parts Kiting. Provided technical
management for a technician and a junior engineer.
Fairchild Communications and Electronics, Germantown, Maryland (2 years)
Designed, developed, and debugged three subsystems of an aircraft camera controller. Extensive use was made of
Programmable Logic Devices to meet density and flexibility requirements. Responsibilities also included worst case timing
analysis, testability analysis, and Built-In-Test design and analysis.
Compression Techniques Corporation, Vienna, Virginia (6 months)
Managed the design and development of the Digital Access and Cross Connect system, which switched and combined up to 64
T1 streams. Performed overall system specification, design, and architecture, and detail design of the switching matrix, system
timing, and fault detection. Selected master CPU (80C86) and supervised detail design of the T1 interface unit. Supervised a
junior engineer and a technician in addition to being an individual contributor.
Access Engineering Corporation, Reston, Virginia (18 months)
Designed direct sequence Spread Spectrum modulator for a 2400 BPS data-over-voice (DOV) MODEM. Designed and
developed a 19.2 KBPS PSK DOV MODEM, which provided for integration of the spread spectrum modulator. Also, performed
preliminary design for an 80 KBPS DOV MODEM as a transitional ISDN product.
RIXON, Inc., Silver Spring, Maryland (2 years)
Designed telecommunications Modems including LSI/MSI digital design, embedded processors, analog signal processing, and
A/D and D/A conversion. Managed product development projects, which involved product definition, planning, generation of
schedules and budgets, and tracking project progress.