| A Sample Test Bench |
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--**************************************************************************
-- Thomas McGonigle
-- A State MAchine Example
--**************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.numeric_std.all;
--**************************************************************************
entity MY_SM is
port(RESET_n : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Start_State_Machine : in STD_LOGIC;
State_Advance_Signal : in STD_LOGIC;
Restart_SM_Signal : in STD_LOGIC;
SM_Output_1 : out STD_LOGIC;
SM_Output_2 : out STD_LOGIC;
SM_Output_3 : out STD_LOGIC
);
end MY_SM;
--**************************************************************************
architecture MY_SM_ARCH of MY_SM is
--State machine Signals
type state_values is (Idle, State_A, State_B, State_C, State_D, State_E,
State_F, State_G);
signal pres_state, next_state : state_values;
signal State_Change_Signal : STD_LOGIC;
---------------------------------------------------------------------------
begin --Begin Architecture
--A process to cause the state to change
----------------------------------------------
Change_State : process(CLOCK, RESET_n, next_state)
begin
if (RESET_n = '0') then
pres_state <= Idle;
elsif rising_edge (CLOCK) then
pres_state <= next_state;
end if;
end process Change_State;
----------------------------------------------
--A process to define State Transitions and Outputs
Define_State_Changes : process (Clock) --(RESET_n, CLOCK, Start_State_Machine, pres_state,
State_Advance_Signal, Restart_SM_Signal)
begin
case pres_state is
when Idle => --Start everything when start bit is detected.
if Start_State_Machine = '1' then
next_state <= State_A ;
else
next_state <= Idle;
end if;
-----
SM_Output_1 <= '0';
SM_Output_2 <= '0';
SM_Output_3 <= '0';
-------------
when State_A =>
SM_Output_1 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_B;
else
next_state <= State_A ;
end if;
-------------
when State_B =>
SM_Output_1 <= '0';
SM_Output_2 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_C;
else
next_state <= State_B ;
end if;
-------------
when State_C =>
SM_Output_1 <= '1';
SM_Output_2 <= '1';
SM_Output_3 <= '0';
-----
if State_Advance_Signal = '1' then
next_state <= State_D;
else
next_state <= State_C ;
end if;
-------------
when State_D =>
SM_Output_1 <= '0';
SM_Output_2 <= '0';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_E;
else
next_state <= State_D ;
end if;
-------------
when State_E =>
SM_Output_1 <= '1';
SM_Output_2 <= '0';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_F;
else
next_state <= State_E ;
end if;
-------------
when State_F =>
SM_Output_1 <= '0';
SM_Output_2 <= '1';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_G;
else
next_state <= State_F ;
end if;
-------------
when State_G =>
SM_Output_1 <= '1';
SM_Output_2 <= '1';
SM_Output_3 <= '1';
-----
if Restart_SM_Signal = '1' then
next_state <= Idle;
else
next_state <= State_G;
end if;
-------------
end case;
end process Define_State_Changes;
--------------------------------------------------------------------
end MY_SM_ARCH;
-- Thomas McGonigle
-- A State MAchine Example
--**************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.numeric_std.all;
--**************************************************************************
entity MY_SM is
port(RESET_n : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Start_State_Machine : in STD_LOGIC;
State_Advance_Signal : in STD_LOGIC;
Restart_SM_Signal : in STD_LOGIC;
SM_Output_1 : out STD_LOGIC;
SM_Output_2 : out STD_LOGIC;
SM_Output_3 : out STD_LOGIC
);
end MY_SM;
--**************************************************************************
architecture MY_SM_ARCH of MY_SM is
--State machine Signals
type state_values is (Idle, State_A, State_B, State_C, State_D, State_E,
State_F, State_G);
signal pres_state, next_state : state_values;
signal State_Change_Signal : STD_LOGIC;
---------------------------------------------------------------------------
begin --Begin Architecture
--A process to cause the state to change
----------------------------------------------
Change_State : process(CLOCK, RESET_n, next_state)
begin
if (RESET_n = '0') then
pres_state <= Idle;
elsif rising_edge (CLOCK) then
pres_state <= next_state;
end if;
end process Change_State;
----------------------------------------------
--A process to define State Transitions and Outputs
Define_State_Changes : process (Clock) --(RESET_n, CLOCK, Start_State_Machine, pres_state,
State_Advance_Signal, Restart_SM_Signal)
begin
case pres_state is
when Idle => --Start everything when start bit is detected.
if Start_State_Machine = '1' then
next_state <= State_A ;
else
next_state <= Idle;
end if;
-----
SM_Output_1 <= '0';
SM_Output_2 <= '0';
SM_Output_3 <= '0';
-------------
when State_A =>
SM_Output_1 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_B;
else
next_state <= State_A ;
end if;
-------------
when State_B =>
SM_Output_1 <= '0';
SM_Output_2 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_C;
else
next_state <= State_B ;
end if;
-------------
when State_C =>
SM_Output_1 <= '1';
SM_Output_2 <= '1';
SM_Output_3 <= '0';
-----
if State_Advance_Signal = '1' then
next_state <= State_D;
else
next_state <= State_C ;
end if;
-------------
when State_D =>
SM_Output_1 <= '0';
SM_Output_2 <= '0';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_E;
else
next_state <= State_D ;
end if;
-------------
when State_E =>
SM_Output_1 <= '1';
SM_Output_2 <= '0';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_F;
else
next_state <= State_E ;
end if;
-------------
when State_F =>
SM_Output_1 <= '0';
SM_Output_2 <= '1';
SM_Output_3 <= '1';
-----
if State_Advance_Signal = '1' then
next_state <= State_G;
else
next_state <= State_F ;
end if;
-------------
when State_G =>
SM_Output_1 <= '1';
SM_Output_2 <= '1';
SM_Output_3 <= '1';
-----
if Restart_SM_Signal = '1' then
next_state <= Idle;
else
next_state <= State_G;
end if;
-------------
end case;
end process Define_State_Changes;
--------------------------------------------------------------------
end MY_SM_ARCH;
My experience with using HDLs is that the primary difficulty I have is syntax. Therefore I am presenting a
sample State Machine file to simplify the process. Feel free to use this as a template. If you do use it, I
would appreciate credit for the assistance.
sample State Machine file to simplify the process. Feel free to use this as a template. If you do use it, I
would appreciate credit for the assistance.
--************************************
-- Thomas McGonigle
-- A test bench for a Sample State Machine.
--
--**************************************************************************--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
--**************************************************************************--
entity Sample_State_Machine_tb is
end Sample_State_Machine_tb;
--**************************************************************************--
architecture Sample_State_Machine_tb_ARCH of Sample_State_Machine_tb is
component MY_SM
port(RESET_n : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Start_State_Machine : in STD_LOGIC;
State_Advance_Signal : in STD_LOGIC;
Restart_SM_Signal : in STD_LOGIC;
SM_Output_1 : out STD_LOGIC;
SM_Output_2 : out STD_LOGIC;
SM_Output_3 : out STD_LOGIC
);
end component MY_SM;
-- Constants and signals
constant CLOCK_PERIOD : time := 125 ns;
constant HALF_CLOCK_PERIOD : time := CLOCK_PERIOD/2;
constant ADC_TSAMP : time := CLOCK_PERIOD * 20;
constant ADC_TSAMP_1 : time := CLOCK_PERIOD * 16;
signal RESET_n : STD_LOGIC;
signal CLOCK : STD_LOGIC;
signal Start_State_Machine : STD_LOGIC := 'L';
signal State_Advance_Signal : STD_LOGIC := 'L';
signal Restart_SM_Signal : STD_LOGIC := 'L';
signal SM_Output_1 : STD_LOGIC;
signal SM_Output_2 : STD_LOGIC;
signal SM_Output_3 : STD_LOGIC;
--**************************************************************************--
begin --Begin Architecture
----------------------------------------------------------------
-- Unit Under Test MY_SM
UUT: MY_SM
port map(
RESET_n => RESET_n,
CLOCK => CLOCK,
Start_State_Machine => Start_State_Machine,
State_Advance_Signal => State_Advance_Signal,
Restart_SM_Signal => Restart_SM_Signal,
SM_Output_1 => SM_Output_1,
SM_Output_2 => SM_Output_2,
SM_Output_3 => SM_Output_3);
--------------------------------------------------------
-- Generate active low reset
gen_reset : process
begin
RESET_n <= '0';
wait for 65 ns;
RESET_n <= '1';
wait;
end process gen_reset;
-----------------------------------------------------
-- Generate clock
gen_clock : process
begin
CLOCK <= '0';
wait for HALF_CLOCK_PERIOD;
CLOCK <= '1';
wait for HALF_CLOCK_PERIOD;
end process gen_clock;
------------------------------------------------------
TEST_DATA_GEN : process
begin
Start_State_Machine <= '0';
State_Advance_Signal <= '0';
Restart_SM_Signal <= '0';
---------------------------
wait for 250 ns;
Start_State_Machine <= '1';--Transition from idle to State_A
wait for 250 ns;
Start_State_Machine <= '0';
wait for 750 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_A to State_B
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_B to State_C
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_C to State_D
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_D to State_E
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_F to State_G
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--In State_G, no transition
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--In State_G, no transition
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
Restart_SM_Signal <= '1';--Return to Idle
wait for 250 ns;
Restart_SM_Signal <= '0';
wait for 500 ns;
wait;
---------------------------
end process TEST_DATA_GEN;
--------------------------------------------------
end Sample_State_Machine_tb_ARCH;
-- Thomas McGonigle
-- A test bench for a Sample State Machine.
--
--**************************************************************************--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
--**************************************************************************--
entity Sample_State_Machine_tb is
end Sample_State_Machine_tb;
--**************************************************************************--
architecture Sample_State_Machine_tb_ARCH of Sample_State_Machine_tb is
component MY_SM
port(RESET_n : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Start_State_Machine : in STD_LOGIC;
State_Advance_Signal : in STD_LOGIC;
Restart_SM_Signal : in STD_LOGIC;
SM_Output_1 : out STD_LOGIC;
SM_Output_2 : out STD_LOGIC;
SM_Output_3 : out STD_LOGIC
);
end component MY_SM;
-- Constants and signals
constant CLOCK_PERIOD : time := 125 ns;
constant HALF_CLOCK_PERIOD : time := CLOCK_PERIOD/2;
constant ADC_TSAMP : time := CLOCK_PERIOD * 20;
constant ADC_TSAMP_1 : time := CLOCK_PERIOD * 16;
signal RESET_n : STD_LOGIC;
signal CLOCK : STD_LOGIC;
signal Start_State_Machine : STD_LOGIC := 'L';
signal State_Advance_Signal : STD_LOGIC := 'L';
signal Restart_SM_Signal : STD_LOGIC := 'L';
signal SM_Output_1 : STD_LOGIC;
signal SM_Output_2 : STD_LOGIC;
signal SM_Output_3 : STD_LOGIC;
--**************************************************************************--
begin --Begin Architecture
----------------------------------------------------------------
-- Unit Under Test MY_SM
UUT: MY_SM
port map(
RESET_n => RESET_n,
CLOCK => CLOCK,
Start_State_Machine => Start_State_Machine,
State_Advance_Signal => State_Advance_Signal,
Restart_SM_Signal => Restart_SM_Signal,
SM_Output_1 => SM_Output_1,
SM_Output_2 => SM_Output_2,
SM_Output_3 => SM_Output_3);
--------------------------------------------------------
-- Generate active low reset
gen_reset : process
begin
RESET_n <= '0';
wait for 65 ns;
RESET_n <= '1';
wait;
end process gen_reset;
-----------------------------------------------------
-- Generate clock
gen_clock : process
begin
CLOCK <= '0';
wait for HALF_CLOCK_PERIOD;
CLOCK <= '1';
wait for HALF_CLOCK_PERIOD;
end process gen_clock;
------------------------------------------------------
TEST_DATA_GEN : process
begin
Start_State_Machine <= '0';
State_Advance_Signal <= '0';
Restart_SM_Signal <= '0';
---------------------------
wait for 250 ns;
Start_State_Machine <= '1';--Transition from idle to State_A
wait for 250 ns;
Start_State_Machine <= '0';
wait for 750 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_A to State_B
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_B to State_C
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_C to State_D
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_D to State_E
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--Transition from State_F to State_G
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--In State_G, no transition
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
State_Advance_Signal <= '1';--In State_G, no transition
wait for 250 ns;
State_Advance_Signal <= '0';
wait for 500 ns;
---------------------------
Restart_SM_Signal <= '1';--Return to Idle
wait for 250 ns;
Restart_SM_Signal <= '0';
wait for 500 ns;
wait;
---------------------------
end process TEST_DATA_GEN;
--------------------------------------------------
end Sample_State_Machine_tb_ARCH;
| A Sample State Machine |